1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for the same.
2. Description of the Related Art
Conventionally, a logic cell array is known. In the logic cell array, a plurality of cells are arranged in an array in a lower layer, and a wiring layer is formed on the lower layer to connect the plurality of cells and thereby to form a logic circuit. Thus, a semiconductor device can be manufactured to have a desired function. In one of such logic cell arrays, logic cells having functional blocks such as a multiplexer, a flip-flop, and an inverter are arranged.
For example, in Japanese Laid Open Patent application (JP-P2001-523048A corresponding to WO99/25023) is disclosed ASIC wiring architecture, in which various IC devices are mutually connected to form a customized circuit. FIG. 1 is a logic notation showing a circuit of a logic cell disclosed in that conventional example. The logic cell is composed of a 4-input and 1-output multiplexer. The multiplexer has four data input terminals D0, D1, D2 and D3, two selection terminals S0 and S1 and one output terminal P.
FIG. 2 shows the arrangement of each terminal of the logic cell. Each of the terminals D0, D1, D2, D3, S0, S1 and P is composed of a pair of terminals (vias), between which a power supply wiring line pattern VDD and a ground wiring line pattern GND are put. Each pair of terminals is provided in parallel to the power supply wiring line pattern VDD and the ground wiring line pattern GND, and the terminals of each pair have the same potential.
In the above-described conventional logic cell, some of the input terminals D0, D1, D2, D3, S1 and S2 are connected with the power supply wiring line pattern VDD or the ground wiring line pattern GND in order to realize a desired logical function. For this reason, the two terminals with the same potential are provided on either side of the power supply wiring line pattern VDD and the ground wiring line pattern GND, as described above. Two horizontal tracks are occupied irrespective of the use/non-use of the terminals in the logic cell.
Also, the logic cell has only the terminals necessary to realize a multiplexer function. Therefore, the logic circuit to be realized using the multiplexer is limited.
Moreover, the positions for the terminals to be arranged are not especially considered. For this reason, it is required to provide a bypass wiring line pattern except for a case to apply the same potential to the adjacent input terminals. Therefore, the wiring line pattern to form the logic cell for a desired logical function becomes complicated. As a result, the wiring line area between the logic cells is restricted and causes the deterioration of the electric characteristic and the workability of wiring line through the bypassing of the wiring line.